Bilayer tungsten diselenide transistors with ON-state present densities over 1.5 milliamperes per micrometer

Bilayer tungsten diselenide transistors with ON-state current densities over 1.5 milliamperes per micrometer

Electrical traits of the sub-100 nm bilayer WSe2 transistors. a, Schematic illustration of the method circulate to type sub-100 nm channel size bilayer WSe2 transistors with artificial VSe2 vdW contacts by way of managed crack formation. b, Optical microscopy picture of a pair of hexagonal VSe2 domains on the WSe2 with an obvious nanogap. Scale bars: 5 μm. c,d, SEM photos of the bilayer WSe2 transistors with 76 nm and 20 nm channel lengths. Scale bars: 100 nm. d,g, Output traits of the 76 nm and 20 nm WSe2 transistors at numerous back-gate voltages with a step of 5 V. e,h, Transfer curves of the 76 nm and 20 nm bilayer WSe2 transistors at numerous bias voltages. Credit: Wu et al.

2D semiconductors might have notable benefits over standard bulk semiconductors, equivalent to silicon. Most notably, their better resistance to short-channel results might make them significantly promising for the event of extremely performing transistors, that are essential parts of all digital units.

Researchers at Hunan University have lately developed extremely performing transistors primarily based on bilayer tungsten diselenide, an inorganic 2D compound with semiconducting properties. These transistors, launched in a paper printed in Nature Electronics, was discovered to carry out in addition to present silicon transistors with comparable channel lengths and driving voltages.

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When evaluating transistors primarily based on 2D semiconductors, engineers can take into account totally different parameters, together with their provider mobility and contact resistance. These two values, nonetheless, are mere estimations that may be miscalculated or misinterpreted, leading to inconsistent estimations of a tool’s efficiency.

The ON-state current density, the quantity of electrical present flowing by way of a particular space whereas a tool is working, has been discovered to be a much more dependable analysis parameter. In their examine, the researchers thus particularly targeted on growing a transistor that had an ON-state present density akin to that of comparable silicon-based units.

“ON-state present density (Ion) or saturation present density is a more direct and reliable measure of assessing transistors with 2D semiconductors,” Xidong Duan, one of many researchers who carried out the examine, advised TechXplore. “It remains an open question whether 2D transistors may match, compete or surpass the state-of-art silicon transistors. To answer such question is essential for inspiring more serious interest from the industry community.”

Most 2D transistors developed up to now exhibit an Ion worth that’s considerably inferior to these of silicon units with comparable channel lengths (Lch) and drain-source bias (Vds). This in the end limits their potential for real-world, sensible functions.

In their earlier research, Duan and his colleagues synthesized ultra-thin 2D metallic and in-situ grown 2D metallic/semiconductor heterojunctions to construct prime quality field-effect transistors. In addition, they created damage-free van der Waals (vdW) electrical contacts that may very well be used to characterize the intrinsic properties of 2D semiconductors.

“Although 2D metals, such as vdW electrical contacts could improve the performance of 2D semiconductors devices, such excellent electrical properties were achieved with a relatively long channel length, while ultrashort channel devices with vdW electrical contact for evaluating the performance of 2D semiconductors still presented challenges,” Duan stated. “The fabrication of ultrashort channel devices often requires aggressive high-resolution lithography and metallization processes, which could introduce undesired contaminations or damages to the atomically thin 2DSCs, and thus seriously compromising their electronic performance.”

Building on their earlier findings, Duan and his colleagues utilized a pure crack formation course of to create a spot between merged VSe2 domains grown on bilayer WSe2. This allowed them to develop ultrashort channel bilayer WSe2 transistors with optimized artificial vdW contacts, reaching a record-high ON-state present density of 1.72 mA/μm and a lowest linear resistance of 0.50 kΩ·μm at room temperature.

“Our results demonstrate for the first time that 2D transistors can deliver competitive current density at a comparable channel length and driving voltage when comparing to the traditional Si transistors,” Duan stated. “It gave a positive answer to the long-standing question in the field of “whether or not 2D transistors can obtain comparable or higher efficiency than the silicon transistors.”

So far, most approaches for fabricating units with ultrashort channels concerned the usage of aggressive methods, together with high-resolution lithography and metallization processes. While these methods might be efficient, additionally they introduce undesired contaminations or harm the anatomically skinny 2DSCs, which may significantly compromise the units’ digital efficiency.

When fabricating their transistor, Duan and his colleagues thus determined to take a distinct method. More particularly, they used a clear vdW contact and ultrashort channel, which was outlined by the thermal stress-controlled nanocrack formation. This allowed them to retain the WSe2 transistor’s unique construction and efficiency as a lot as doable.

“The obtained ultrashort channels are generally rather straight, distinct from lithographically defined electrodes that often exhibit finite line edge roughness, which creates a good condition for exploring the limit performance of WSe2 transistors,” Duan defined. “In addition, bilayer WSe2 materials typically have smaller bandgaps and better immunity to the fabrication induced damages or interfacial scattering, compared with their monolayer counterpart.”

In preliminary evaluations, the researchers noticed outstanding on-state present densities of 1.0–1.7 mA μm-1 in sub-100 nm bilayer WSe2 transistors, exceeding the essential present density goal for 2D transistors (i.e., 1.5 mA μm-1). Their findings might thus have worthwhile functions for the sector of electronics engineering, as they present that transistors primarily based on 2D semiconductors can ship aggressive present densities at channel lengths and driving voltages which can be akin to these of silicon-based transistors.

“We believe the realization of the current density beyond the 1.5 mA/mm has made a positive answer to the long-standing question in the field of ‘whether 2D transistors can achieve comparable or better performance than the silicon transistors,'” Duan stated. “It could inspire additional efforts from both the academic and industry community to promote the development of a new generation of 2D semiconductor and chip technology after silicon-based semiconductor.”

In the longer term, the latest work by Duan and his colleagues might encourage different groups to develop comparable units primarily based on WSe2 or different 2D semiconductors. However, the units they developed up to now aren’t but totally optimized. For occasion, the crew was pressured to create them utilizing comparatively thick back-gate dielectrics (i.e., 70 nm SiNx), as high-quality dielectrics might be onerous to combine on dangling-bond-free 2D surfaces. The dielectrics they used have a quite small gate-capacitance, which may restrict the system’s gate coupling effectivity and the extent to which gates might be managed.

“Our next studies will focus on developing high-quality gate dielectrics with minimum equivalent oxide thickness and minimum interface state to achieve stronger gate control, higher current (closer to the long-term targets of 3.0 mA μm−1), smaller subthreshold swing (closer to the theoretical value 60 mV/dec) and lower Ioff (100 pA μm−1), making the overall key performance parameters of 2D transistors have obvious advantages over silicon transistors,” Duan added. “In addition, we plan to further improve the integration of 2D transistors to promote the commercial application of 2D transistors by combining the large-area growth of 2D semiconductor TMD and 2D metal, advanced lithography process to pattern 2D metal contact arrays and scalable vdW integration process.”

An indium oxide-based transistor created using atomic layer deposition

More info:
Ruixia Wu et al, Bilayer tungsten diselenide transistors with on-state currents exceeding 1.5 milliamperes per micrometre, Nature Electronics (2022). DOI: 10.1038/s41928-022-00800-3

Yuan Liu et al, Promises and prospects of two-dimensional transistors, Nature (2021). DOI: 10.1038/s41586-021-03339-z

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